Join Silicon Interfaces as a Front-end RTL Design Engineer in Mumbai. Work on cutting-edge VLSI projects using SystemVerilog/UVM, protocols, low power, and DFT. 1-6 years experience required, strict graduation year criteria. Apply after mandatory online assessment.

About the Company

Silicon Interfaces is an AI-ML enabled semiconductor services company specializing in IPs, ASICs, and multicore designs. With a global footprint spanning North America, Europe, and Asia Pacific, the company delivers functional verification, low power design, DFT, and advanced methodology solutions using industry standards like UVM, Portable Stimulus (PSS/DSL), and UPF. Their state-of-the-art VLSI Design Centers are headquartered in Mumbai, India, and they serve clients through on-site, remote, and offshore deployments. The company is committed to innovation in data communications, wired and wireless networking, and interconnect technologies.

Role Overview

Silicon Interfaces is seeking a Front-end RTL Design Engineer with 1–6 years of experience (strictly 2023 or earlier graduates, or Master’s 2024). The role involves working as a team member on specialized projects in SystemVerilog/UVM methodology, Portable Stimulus Standards (PSS) based Domain Specific Language (DSL), fault simulation, multi-core processor verification, and low power designs. The position is based in Mumbai and requires full-time work from office (no remote training or work). You will be expected to join at the earliest and must reside in Mumbai to attend offices in Vashi (and potentially Andheri for some projects). An assessment test is mandatory before application.

Key Responsibilities

• Design and verify RTL logic using SystemVerilog and UVM for complex VLSI projects.
• Develop and execute verification plans, testbenches, and coverage closure for protocols such as I2C, USB, Ethernet, 802.11, PCIe, and AMBA (AXI/CHI).
• Contribute to Portable Stimulus Standards (PSS) based DSL for cross-platform reuse.
• Perform low power verification using UPF, fault simulation, and DFT.
• Work on multi-core processor verification and low power designs in data communications and networking domains.
• Utilize Linux environment, Gvim/VI, and shell scripting for development and debugging.
• Collaborate with global teams via VPN-based logins and on-site deployments as needed.
• Follow strict methodologies and meet project milestones in a fast-paced VLSI environment.

Tech Stack

• SystemVerilog, UVM
• Logic Design
• Protocols: I2C, USB, Ethernet, 802.11, PCIe, AMBA/AXI/CHI
• Linux, Gvim/VI, Shell Scripting
• PSS/DSL, UPF, DFT, Fault Simulation
• Low Power Design Techniques

BE/B.Tech/ME/M.Tech in Electronics and/or Communications Engineering from Tier 1 or Tier 2 colleges (strictly 2023 or earlier graduates or Master’s 2024). 1–6 years of experience in RTL design and verification. Proficiency in SystemVerilog/UVM and protocols. Strong knowledge of Linux and scripting. Must be willing to work from office in Mumbai and take an online assessment test.

Leave encashment, Paid sick time, Paid time off, Provident Fund