Define and drive SI/PI strategy across SiMa's entire MLSoC product line. Own architecture, simulation flows, and lab validation for high-speed interfaces (PCIe Gen5, DDR5, MIPI, USB 3.x). Lead margin closure and compliance for production designs.

About the Company: SiMa Technologies is a venture-backed AI and machine learning semiconductor startup headquartered in Bangalore, India, with a global footprint. The company specializes in designing innovative MLSoC (Machine Learning System-on-Chip) solutions that deliver high-performance, power-efficient edge AI processing. Their platforms are used in robotics, autonomous vehicles, smart cameras, and industrial IoT applications. As a fast-growing company at the forefront of hardware innovation, SiMa is committed to pushing the boundaries of signal and power integrity in high-speed digital systems.

Role Overview: The Principal Engineer, System HW Design - SI/PI is a senior technical leadership role within the Systems Hardware Engineering Team. This position is responsible for defining and driving the signal integrity (SI) and power integrity (PI) strategy across the entire product line of SiMa's MLSoC solutions. The role involves working on cutting-edge high-speed designs including System-on-Modules, PCIe add-in cards, chip-down BGA reference designs, and full development platforms. The engineer will own the SI/PI architecture, simulation methodologies, and lab validation processes to ensure reliable high-speed signaling and power delivery. This is a pivotal role that sets technical standards and direction for the hardware organization, requiring deep expertise in high-speed interfaces, power delivery networks, and industry compliance.

Key Responsibilities:

• Define and document SI/PI architecture, design guidelines, and sign-off criteria for all SiMa product platforms including SoM, PCIe HHHL cards, chip-down BGA, and DevKit carriers.
• Serve as the technical specialist for high-speed interface margin closure on PCIe Gen5 (up to 32 GT/s per lane), MIPI CSI/DSI (C-PHY/D-PHY), USB 3.x/Type-C, 10 Gigabit Ethernet SerDes, and LPDDR memory channels.
• Drive PCB stack-up, impedance, and channel budget decisions across multiple concurrent board programs, balancing cost, manufacturability, and signal margin.
• Own the power delivery network (PDN) architecture for high-transient-current AI accelerator silicon, setting design targets and review standards.
• Define connector and interconnect strategy across product generations for board-to-board, M.2 NVMe, and PCIe edge-card interfaces.
• Establish lab validation standards and lead escalation-level debug for the most challenging SI/PI issues during bring-up.
• Own the SI/PI simulation tool strategy and flow, evaluating and selecting tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, and building reusable methodology assets.
• Oversee compliance testing for PCIe-SIG, USB-IF, and MIPI Alliance on production and pre-production boards.
• Engage with component vendors and standards bodies to stay ahead of emerging high-speed interface requirements.

Tech Stack:

• High-speed interfaces: PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, USB 3.x/Type-C, MIPI D-PHY/C-PHY, 10 Gigabit Ethernet SerDes.
• Simulation tools: Ansys HFSS, Ansys SIwave, Cadence Sigrity, Cadence Clarity, Keysight ADS.
• Lab equipment: VNA, TDR, high-bandwidth oscilloscopes.
• Compliance standards: PCIe-SIG, USB-IF, MIPI Alliance.
• PCB design: stack-up design, transmission line theory, S-parameters, channel modeling, PDN design.
• Additional: ASIC characterization, PCB manufacturing, assembly, test, quality & reliability.

Bachelor's in Electrical Engineering or related field (Master's preferred) with 15+ years of industry experience in signal and power integrity engineering for high-speed digital systems. Deep expertise in PCIe Gen4/Gen5, DDR4/DDR5/LPDDR, USB 3.x, and MIPI D-PHY/C-PHY signaling. Proven track record owning PDN architecture for high-power SoCs/ASICs. Expert-level proficiency with SI/PI EDA tools (Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS). Extensive hands-on lab validation experience (VNA, TDR, high-bandwidth oscilloscopes). Strong knowledge of PCIe-SIG, USB-IF, MIPI Alliance compliance standards. Demonstrated ability to set technical direction and mentor senior engineers. Cross-functional leadership skills.

Competitive equity package, performance bonuses, health insurance, flexible work hours, and opportunities to work with cutting-edge AI hardware technology.