Join Quadric as a Senior Design Verification Engineer and lead the charge in architecting a groundbreaking SoC verification environment.

About the Company

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. The technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems. Founded by technologists from MIT and Carnegie Mellon, Quadric operates as a well-funded growth-stage semiconductor IP company with a growing licensing business.

Role Overview

As a Senior Design Verification Engineer at Quadric, you will be pivotal in the development of a revolutionary processor-based SoC architecture. You will take technical leadership in architecting and building the SoC-level verification environment from the ground up. The role requires close collaboration with architects, hardware engineers, and software teams to ensure high-quality and complete verification coverage for next-generation GPNPU-based SoCs.

Key Responsibilities

• Testbench Architecture & Test Plan Development: Architect and build scratch-built testbenches for SoC-level verification of GPNPU-based SoCs. Collaborate cross-functionally to document comprehensive verification test plans and implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.

• Test Execution & Verification Coverage: Develop directed and random drivers, as well as assembly or C++ programs, to effectively stress-test SoC subsystems and integration. Verify complex SoC subsystems, including 3rd-party IP like NoC, PCIe/UCIe, and DDR, utilizing VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites. Track, analyze, and communicate verification progress using functional and code coverage metrics.

Tech Stack

• Languages: SystemVerilog, Verilog, C++, Assembly
• Scripting: Python
• Tools: VCS, UVM, Verification IP, Co-Simulation environments
• Integrations: PCIe, NoC, DDR

Success Metrics

Within your first 6 to 12 months, you will achieve key milestones including building a fully functional SoC-level UVM verification environment, achieving target coverage metrics across critical SoC subsystems, and establishing robust co-simulation pipelines.

This role is located in Pune, India and offers a competitive salary, approximately ₹1,50,000 - ₹2,20,000 per month, reflecting the high demand for specialized skills in the semiconductor industry.

Quadric is proud to be an equal opportunity employer, committed to creating an inclusive environment. We welcome applications from individuals who possess the potential and eagerness to learn, regardless of exact matches with every qualification.

Requirements

• Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.
• Deep expertise in UVM methodology and leading SoC-level verification practices.
• Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.
• Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
• Strong computer architecture background with experience in VCS and Verilog/C Co-Simulation.

Benefits

• Competitive salary.
• Medical, dental, and vision insurance.
• Equity with the business.
• Paid Parental Leave.
• PF Retirement Plan.
• Flexible PTO.
• Winter holiday shutdown.
• Catered lunch each day in our office.
• Collaborative, low-ego culture with significant ownership and impact.
• A work culture focused on innovative disruption.